The characteristic that defines ferroelectricity is its spontaneous polarization which can be reversed by an electric field. Various ferroelectric materials are known, such as the PZT family of lead zirconate and titanate compounds, Phase III potassium nitride, bismuth titanate, or the like, each of which has a Perovskite structure. When the proper electrical field is applied to a ferroelectric material, its polarization is arranged in the same direction. The ferroelectric material remains in essentially the same polarization when the electric field is removed. This phenomena is known the spontaneous polarization. Because the direction of an applied electric field can change polarizations and the ferroelectric material has two threshold voltages for the reverse of its polarization, it can be thought of as a bi-stable capacitor.
Generally, in areas that require high speed and symmetrical read/write characteristics and extremely high endurance, a volatile SRAM or DRAM is used. In areas where a nonvolatile semiconductor memory is desired, an EPROM, EEPROM or flash memory is used although their characteristics are inferior in write speed and endurance to DRAMS and SRAMS. When large capacity and low cost are both desired, magnetic memories are used. Ferroelectric memory has the potential to replace such all existing electronic memories (i.e., semiconductor memories and magnetic memories).
Referring to FIG. 1A, there is shown a ferroelectric memory cell MC having a cell capacitor C.sub.F and an access transistor Tr acting as a switching device. Capacitor C.sub.F comprises a plate made of ferroelectric material used as a capacitor dielectric and two plate electrodes formed on the opposite two surfaces of the plate. One plate electrode of the ferroelectric capacitor C.sub.F is coupled via the source-drain conduction path of the access transistor Tr to a bit line BL, and the other plate electrode of the capacitor C.sub.F is coupled to a plate line PL. The gate electrode of the transistor Tr is coupled to a word line WL.
When a voltage is applied to the ferroelectric plate of the capacitor C.sub.F, the plate is polarized in the direction of the electric field. The switching threshold for changing the polarization state of the ferroelectric capacitor C.sub.F is defined as the coercive voltage. A ferroelectric material has a polarization-voltage characteristic which exhibits hysteresis, and the flow of current to the capacitor C.sub.F depends on its polarization state. If the voltage applied to the capacitor C.sub.F is greater than the coercive voltage, then the capacitor C.sub.F may change polarization states depending on the polarity of the applied voltage. Once polarized by applying a voltage to it in one direction or the opposite direction, the ferroelectric capacitor C.sub.F remains polarized even after the application of the voltage is stopped. Thus, the ferroelectric capacitor C.sub.F can store either logic "one" or logic "zero" according to the state of polarization of the ferroelectric material between two plate electrodes.
FIGS. 1B and 1C illustrate hysteresis curves of polarization of the ferroelectric material in capacitor C.sub.F in accordance with logic states thereof. In each FIG. 1B or 1C, the abscissa (or X axis) represents an external voltage V applied across the two plate electrodes of the capacitor C.sub.F, and the ordinate (or Y axis) represents polarization charge Q on the ferroelectric material between two plate electrodes. Referring to FIGS. 1B and 1C, it will be seen that two stable states at points "a" and "e" on the hysteresis curve exist even when no voltage is applied across the ferroelectric capacitor C.sub.F. This is because the prior history of the voltage applied across the capacitor C.sub.F determines the stable state `a` or `e` which results when voltage is removed. So, point `a` can represent logic "1", and point `e` can represent logic "0".
When a voltage Ve is applied to one plate electrode of the ferroelectric capacitor C.sub.F, namely, when a voltage Ve is applied to the plate line PL in a negative direction while transistor Tr is conducting, the charge stored in the capacitor C.sub.F is fed out onto bit line BL. The amount of the charge is Q1 if the ferroelectric is in the state at point `a` (i.e., if logic "1" is stored in the capacitor C.sub.F) as shown in FIG. 1B, but the amount of the charge is Q0 if the ferroelectric is in the state at point `e` (i.e., if a logic "0" is stored in the capacitor C.sub.F) as shown FIG. 1C. A resulting change in voltage on the bit line BL is detected by a differential sense amplifier (not shown) by comparison with a reference voltage. The reference voltage is an intermediate between a voltage developed on bit line BL by the charge Q1 and another voltage developed on bit line BL by the charge Q0.
When the voltage--Ve is applied across a ferroelectric capacitor C.sub.F in order to read the data from the capacitor, the ferroelectric capacitor is not reversely polarized if the capacitor has been polarized in a first direction and stores a "0" bit (point `e`). However, when the voltage--Ve is applied across the ferroelectric capacitor in order to read data from the capacitor, the ferroelectric capacitor is reversely polarized and its data state moves to point `e` if the capacitor has been polarized in a second direction and stores a "1" bit (point `a`). In this case, the plate may be polarized in the first direction (point `a` corresponding to a logic "0") after the "1" bit has been read from the ferroelectric capacitor. To retain correct data, therefore, the capacitor should be polarized in the second direction again after the "1" bit has been read from the capacitor.
FIG. 2A illustrates a core portion of a ferroelectric memory device in accordance with prior art, for example, U.S. Pat. No. 5,592,410 by Verhaeghe et al. The prior art memory device includes a ferroelectric memory cell array 10, a row decoder 20, sense amplifiers SA.sub.-- 0, SA.sub.-- 1, etc., bit lines BL.sub.-- 0, BL.sub.-- 1, etc., word lines WL.sub.-- 0, WL.sub.-- 1, etc., and plate lines PL.sub.-- 0, PL.sub.-- 1, etc., substantially running in parallel to the word lines WL.sub.-- 0, WL.sub.-- 1, etc. The memory cells MC00, MC01, MC10, MC11, etc., are arranged in intersecting rows and columns. A memory cell MCij has a ferroelectric cell capacitor C.sub.F and an access transistor Tr. One plate electrode of the capacitor C.sub.F is coupled via the source-drain conduction path of the access transistor to a corresponding bit line, and the other plate electrode of the capacitor C.sub.F is coupled to a corresponding plate line. The gate electrode of the transistor Tr is coupled to a corresponding word line.
In the above-mentioned prior art memory device, however, since a row decoder is adopted for driving the word lines and plate lines simultaneously, the chip area may be increased which may reduce the integration. Also, the number of cells that a word line can drive may usually be limited to 32 cells/PL or 64 cells/PL due to RC delay of PL driving signal.
FIG. 2B illustrates a portion of another prior art ferroelectric memory device. Such a prior art arrangement may be suitable for higher integration and operating speed, which is disclosed in, for example, U.S. Pat. Nos. 5,598,366 by Kraus et al. and 5,373,463 by Jones Jr. Referring to FIG. 2B, this memory device has the same structure as the device of FIG. 2A with the exception that it includes a plate line PL, a control circuit 30 for driving the plate line PL, plate line segments SPL.sub.-- 0, SPL.sub.-- 1, etc., each running in parallel with a corresponding word line and coupled to a predetermined number of cells, and plate select transistors ST0, ST1, etc., for selectively coupling the plate line segments SPL.sub.-- 0, SPL.sub.-- 1, etc., to the plate line PL. The gate electrodes of plate select transistors ST0, ST1, are coupled to corresponding word lines WL.sub.-- 0, WL.sub.-- 1, etc.
When a word line is selected during a read/write operation, a corresponding plate select transistor becomes conducting, so that the plate line and a corresponding plate line segment are coupled to each other via the source-drain conduction path of the plate select transistor. At this time, the remaining plate line segments corresponding to unselected word lines are floated by corresponding coupling transistors which remain non-conducting.
According to this prior art plate line driving technique, there may arise a problem in that the voltages on the floated plate line segments adjacent to the selected plate line are changed on account of their capacitive coupling, causing the sensing margin to be reduced and the data stored in memory cells to be disturbed or destroyed in a worse case.
Also, in prior art data write operation, the data line-to-bit line transmission of write data may be carried out after cell data sensing has been completed. Thus, in case the latch type sense amplifier is used, it may often be needed to invert the data state of the latch amplifier because of disagreement between the sensed cell data and the externally applied write data. To invert the state of the latch amplifier coupled to polysilicon bit lines with relatively large resistance, a large amount of current will be necessary, thereby increasing power consumption of the device.